Refine your search
Collections
Journals
Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Kumar, V. M. Senthil
- CMOS Based Driver Tree Design for Microprocessor Clock Distribution Units Iin Biomedical Image Processing Circuits
Abstract Views :130 |
PDF Views:0
Authors
V. Sujatha
1,
S. Ravindrakumar
2,
D. Sasikala
3,
V. M. Senthil Kumar
4,
N. V. Kousik
5,
Jayasri Subramaniam
6
Affiliations
1 Department of Electronics and Communication Engineering, Shree Sathyam College of Engineering and Technology, IN
2 Department of Biomedical Engineering, Sri Shakthi Institute of Engineering and Technology, IN
3 Department of Electronics and Communication Engineering, Muthayammal Engineering College, IN
4 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
5 Department of School of Computing Science and Engineering, Galgotias University, IN
6 Division of Computing, University of Northampton, GB
1 Department of Electronics and Communication Engineering, Shree Sathyam College of Engineering and Technology, IN
2 Department of Biomedical Engineering, Sri Shakthi Institute of Engineering and Technology, IN
3 Department of Electronics and Communication Engineering, Muthayammal Engineering College, IN
4 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
5 Department of School of Computing Science and Engineering, Galgotias University, IN
6 Division of Computing, University of Northampton, GB
Source
ICTACT Journal on Microelectronics, Vol 7, No 1 (2021), Pagination: 1080-1084Abstract
The transmission of clock signal is done across the integrated circuit in the presence of buffers and wires in synchronous biomedical systems on-chip architectures. This paper presents the investigation of the driver tree architecture to be used in microprocessor and DSP processors for biomedical image processing applications for clock distribution. In system on chip architecture this design plays an important role. Several clock distribution units like parallel, H-Bridge configurations were implemented in past. A new buffer is designed for the improvement of driving capability in clock distribution. This paper presents the CMOS based clock distribution circuit with better power and drive current. The parameters like power and current are investigated. Predictive technology models for CMOS 90nm technology are used.Keywords
CMOS, Current Driver, Clock Driver, H-Bridge, Buffer, Power.
References
- H. Zhu and V. Kursun, “2-Phase High-Frequency Clock Distribution with SPLIT-IO Dual-Vt Repeaters for Suppressed Leakage Currents”, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2932-2935, 2015.
- K. Gundu and V. Kursun, “Low Leakage Clock Tree with Dual-Threshold-Voltage Split Input-Output Repeaters”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 7, pp. 1537-1547, 2019.
- K. Athikulwongse, X. Zhao and S.K. Lim, “Buffered Clock Tree Sizing for Skew Minimization under Power and Thermal Budgets”, Proceedings of IEEE International Conference on Design Automation, pp. 474-479, 2010.
- K. Niitsu, M. Sakurai, N. Harigai, T.J. Yamaguchi and H. Kobayashi, “CMOS Circuits to Measure Timing Jitter using a Self-Referenced Clock and a Cascaded Time Difference Amplifier with Duty-Cycle Compensation”, IEEE Journal on Solid-State Circuits, Vol. 47, No. 11, pp. 2701-2710, 2012.
- L. Ravezzi and H. Partovi, “Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC”, IEEE Journal on Solid-State Circuits, Vol. 50, No. 7, pp. 1702-1710, 2015.
- M. Dave, M. Jain, M.S. Baghini and D. Sharma, “A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 2, pp. 342-353, 2013.
- P. Hao and S. Chen, “Single-Event Transient Susceptibility Analysis and Evaluation Methodology for Clock Distribution Network in the Integrated Circuit Working in Real Time”, IEEE Transactions on Device and Materials Reliability, Vol. 17, No. 3, pp. 539-548, 2017.
- R. Islam and M.R. Guthaus, “CMCS: Current-Mode Clock Synthesis”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 3, pp. 1054-1062, 2017.
- R. Islam, H. Fahmy, P.Y. Lin and M.R. Guthaus, “Differential Current-Mode Clock Distribution”, Proceedings of Midwest Symposium on Circuits and Systems, pp. 1-4, 2015.
- S.J. Park, N. Natu and M. Swaminathan, “Analysis Design and Prototyping of Temperature Resilient Clock Distribution Networks for 3-D ICs”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 5, No. 11, pp. 1669-1678, 2015.
- Todri Sanial and Y. Cheng, “A Study of 3-D Power Delivery Networks with Multiple Clock Domains”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 11, pp. 3218-3231, 2016.
- V.F. Pavlidis, I. Savidis and E.G. Friedman, “Clock Distribution Networks in 3-D Integrated Systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 12, pp. 2256-2266, 2011.
- X. Chen, T. Zhu, W. Davis and P.D. Franzon, “Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 4, No. 11, pp. 1862-1870, 2014.
- X. Zhao, J. Minz and S.K. Lim, “Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) based 3D ICs”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 1, No. 2, pp. 247-259, 2011.
- X.W. Shih and Y.W. Chang, “Fast Timing-Model Independent Buffered Clock-Tree Synthesis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 9, pp. 1393-1404, 2012.
- Ravindrakumar, Joselyn, “Design of Low Power Blink Detector for Minimally Invasive Implantable Stimulator (SOC) using 180nm Technology”, Advances in Intelligent and Soft Computing, 2014.
- Ravindrakumar, Joselyn, “Design of New Implantable Stimulator Chip (SoC) for Non-Invasive/Minimally Invasive Biomedical Application”, Proceedings of International Conference on Communications and Signal Processing, pp. 1-5, 2014.
- V.M. Senthilkumar, A. Muruganandham, S. Ravindrakumar and N.S. Gowri Ganesh, “FINFET Operational Amplifier with Low Offset Noise and High Immunity to Electromagnetic Interference”, Microprocessors and Microsystems, Vol. 71, pp.1-22, 2019.
- V.M. Senthilkumar, S. Ravindrakumar and D. Nithya,“A Vedic Mathematics Based Processor Core for Discrete Wavelet Transform using FinFET and CNTFET Technology for Biomedical Signal Processing”, Microprocessors and Microsystems, Vol. 71, pp.2221-2228, 2019.
- S. Ravindrakumar, “High Speed, Low Matchline Voltage Swing and Search Line Activity TCAM Cell Array Design in 14nm FinFET Technology”, Proceedings of International Conference on Emerging Trends in Electrical, Communication and Information Technologies, pp. 1-12, 2018.
- V.M. Senthilkumar and S. Ravindrakumar, “A Low Power and Area Efficient FinFET Based Approximate Multiplier In 32nm Technology”, Proceedings of International Conference on Soft Computing and Signal Processing, pp. 1-12, 2018.
- M. Senthilkumar and S. Ravindrakumar, “Design of Adiabatic Array Logic Adder using Multigate Device in 32nm FinFET Process Technology”, Journal of Advanced Research in Dynamical and Control Systems, Vol. 22, No. 2, pp. 464-472, 2018.